A hardware multi-pass attribute grammar evaluator

Attribute grammars (AGs) were introduced by Knuth in 1968. The addition of attributes and semantic rules to Context Free Grammars (CFG), augmented their expressional capabilities, making them, by this way, a really useful tool for a considerable number of applications. However, the additional complexity imposed by the added characteristics, dictates the need for hardware solutions for the whole procedure (parsing and attribute evaluation), as an attractive alternative to classical software solutions in order to speed-up the execution time. In this paper, a hardware architecture for a multi-pass attribute evaluation system is presented. The proposed system is based on an efficient combinatorial implementation of Earleys parallel parsing algorithm for the syntax part of the attribute grammar. The semantic part is managed by a special purpose module that traverses the parse tree as many times as needed, in order to evaluate the attributes. The entire system is described in Verilog HDL (Hardware Design Language), simulated for validation, synthesized and tested on a Xilinx FPGA (Field Programmable Gate Arrays) board for various AGs. Our method increases the performance up to three orders of magnitude compared to previous approaches.